For NAND flash memory scaling, there is a planer floating gate (FG) cell in which a planer inter-poly insulating film is formed on a thin-film floating gate. To improve the memory capability of the planer FG cell there has been proposed a cell structure in which a metal layer is formed on the thin-film floating gate with an inter floating-gate dielectric (IFD) layer interposed there between.
With this planer FG cell structure, a metal layer of Ru or the like is formed on a floating gate of polysilicon or the like, and an inter-poly insulating film (high dielectric constant insulating film) of HfOx or the like is formed directly on the metal layer. In this case, the metal is diffused to the side of the inter-poly insulating film and to the side of the floating gate/tunnel film.
This leads to degradation of the insulating properties of the inter-poly insulating film or the tunnel insulating film, and poses a problem of reliability degradation of the memory cell.